Package hardware-multiplier-def: Definition of hardware multiplier devices
Information
| name | hardware-multiplier-def |
| version | 1.12 |
| description | Definition of hardware multiplier devices |
| author | Joe Leslie-Hurd <joe@gilith.com> |
| license | MIT |
| provenance | HOL Light theory extracted on 2014-11-17 |
| checksum | c3fd5683310c2c2512d3d72485f85604d787834c |
| requires | base hardware-adder hardware-bus hardware-counter |
| show | Data.Bool Hardware Number.Natural |
Files
- Package tarball hardware-multiplier-def-1.12.tgz
- Theory source file hardware-multiplier-def.thy (included in the package tarball)
Defined Constants
- Hardware
- Bus
- Bus.multiplier
- SumCarry
- SumCarry.multiplier
- Bus
Theorems
⊦ ∀ld xs xc d ys yc zb zs zc.
SumCarry.multiplier ld xs xc d ys yc zb zs zc ⇔
∃xb ldd xbd.
SumCarry.shiftRight ld xs xc xb ∧ pipe ld d ldd ∧ pipe xb d xbd ∧
Bus.multiplier ldd xbd ys yc zb zs zc
⊦ ∀ld xb ys yc zb zs zc.
Bus.multiplier ld xb ys yc zb zs zc ⇔
∃r sp sq sr cp cq cr yos yoc ps pc sq0 sq1 sr0 sr1 cq0 cq1 cr0 cr1 yos0
yos1 yoc0 yoc1 pc0 pc1 pc2 pc3.
Bus.width ys = r + 1 ∧ Bus.width yc = r + 1 ∧ Bus.width zs = r + 1 ∧
Bus.width zc = r + 1 ∧ Bus.width sp = r + 1 ∧ Bus.width sq = r + 1 ∧
Bus.width sr = r + 1 ∧ Bus.width cp = r + 1 ∧ Bus.width cq = r + 1 ∧
Bus.width cr = r + 1 ∧ Bus.width yos = r + 1 ∧
Bus.width yoc = r + 1 ∧ Bus.width ps = r ∧ Bus.width pc = r + 1 ∧
Bus.wire sq 0 sq0 ∧ Bus.sub sq 1 r sq1 ∧ Bus.sub sr 0 r sr0 ∧
Bus.wire sr r sr1 ∧ Bus.sub cq 0 r cq0 ∧ Bus.wire cq r cq1 ∧
Bus.sub cr 0 r cr0 ∧ Bus.wire cr r cr1 ∧ Bus.wire yos 0 yos0 ∧
Bus.sub yos 1 r yos1 ∧ Bus.sub yoc 0 r yoc0 ∧ Bus.wire yoc r yoc1 ∧
Bus.wire pc 0 pc0 ∧ Bus.sub pc 0 r pc1 ∧ Bus.sub pc 1 r pc2 ∧
Bus.wire pc r pc3 ∧ Bus.case1 ld (Bus.ground (r + 1)) sp sq ∧
Bus.case1 ld (Bus.ground (r + 1)) cp cq ∧
Bus.case1 xb ys (Bus.ground (r + 1)) yos ∧
Bus.case1 xb yc (Bus.ground (r + 1)) yoc ∧ adder2 sq0 yos0 zb pc0 ∧
Bus.adder3 sq1 cq0 yos1 ps pc2 ∧ Bus.adder3 yoc0 ps pc1 sr0 cr0 ∧
adder3 yoc1 cq1 pc3 sr1 cr1 ∧ Bus.connect sr zs ∧ Bus.connect cr zc ∧
Bus.delay sr sp ∧ Bus.delay cr cp
External Type Operators
- →
- bool
- Hardware
- bus
- wire
- Number
- Natural
- natural
- Natural
External Constants
- =
- Data
- Bool
- ∀
- ∧
- ∃
- ⊤
- Bool
- Hardware
- adder2
- adder3
- pipe
- Bus
- Bus.adder3
- Bus.case1
- Bus.connect
- Bus.delay
- Bus.ground
- Bus.sub
- Bus.width
- Bus.wire
- SumCarry
- SumCarry.shiftRight
- Number
- Natural
- +
- bit1
- zero
- Natural
Assumptions
⊦ ⊤
⊦ (∀) = λp. p = λx. ⊤